1. Field of the Invention
The present invention relates to a semiconductor device, more specifically to a transistor for preventing a thermal runaway caused by temperature rise in a bias circuit of the transistor.
2. Description of the Related Art
In case of a field effect transistor (hereinafter, referred to as FET) using a compound semiconductor, there has an advantage to make the limitation of its operating frequency high since the electron mobility of its material is high. However, operating the FET using the compound semiconductor at a high temperature causes a drain current to increase rapidly, so that the transistor breaks down by causing the thermal runaway.
FIG. 11 is a circuit diagram showing a bias circuit of FET in general. Hereinafter, the cause of thermal runaway in the FET using a compound semiconductor will be explained with reference to FIG. 11. For a purpose of setting a DC bias voltage, an FET 101 has a voltage split circuit constituted of a resistors R1 and R2 connected in series between the ground and an external bias-supplying power source Vgg, which supplies a voltage in between the resistors R1 and R2 to a gate G. A gate potential Vg1 of FET 101 in this case is represented by an expression (1) in consideration of a gate current Ig flown into the gate G from a drain. ##EQU1##
The bias circuit of FET shown in FIG. 11 has a characteristic such that a voltage drop increases caused by the resistance component represented by the second term of the expression (1) and the gate potential Vg1 rises, when increasing the gate current Ig. Because of this, when an ambient temperature rises in this case, the increase of a drain current Ids is induced since the gate current Ig increases exponentially. As a result of continuing the self-heat generation and temperature rise caused by the power consumption in the FET, the breakdown of FET occurs by causing the thermal runaway.
In such case of FET using the compound semiconductor, the thermal runaway occurring at the high temperature causes that the practical bias potential or gate potential Vg1 becomes low or shallow, since the gate current Ig increases as well as the voltage drop increases in the bias circuit. Thus, for the purpose of preventing the thermal runaway, the voltage drop of the bias circuit is made small in increasing temperature, thereby the gate potential Vg1 should not become low.
In contrast, a bias circuit of FET has been proposed with a Japanese Patent Application Laid-Open No. Hei4-175002 in which a diode is connected to a gate bias circuit in series and the negative temperature characteristic of the diode is used to reduce the increase of drain current Ids in temperature rise. FIG. 12 is a circuit diagram showing a bias circuit of FET proposed by the gazette. The bias circuit has a diode 103 connected, in forward direction, in series with a resistor R1 of a voltage split circuit constituted with a resistor R2, both the resistors of which are connected in series between a ground potential and a gate bias-supplying power source Vgg, for the purpose of setting a DC bias of an FET 102. The forward direction voltage of diode 103 decreases with the temperature rise to thereby indicate a negative temperature characteristic of approximately -1.5 mV/.degree. C. Therefore, when the temperature increases from the room temperature to 100.degree. C., for example, the voltage drop of diode 103 is decreased to about 0.15 volts. With this decrease of voltage drop at the diode 103, a gate potential Vg1 of FET 102 decreases to thereby reduce the increase of a drain current Ids.
However, in the bias circuit of FET, the reduction of increasing the gate potential Vg1 is not quite sufficient in the temperature rise. FIG. 13 is a graph showing, for example, the temperature dependency of gate current Ig for the FET using a compound semiconductor, that is, a characteristic example showing the gate current Ig (.mu.A) to a channel temperature T (.degree. C.). As shown in FIG. 13, the gate current Ig increases exponentially at 100.degree. C. or over, and it reaches to several hundred times the value of room temperature at 170.degree. C. Assuming that the values of resistors R1 and R2 are 1 k.OMEGA. respectively and the gate current Ig of FET 102 increases up to 900 .mu.A at 170.degree. C. as shown in FIG. 13, the gate potential Vg1 is decreased to 0.45 volts from that at the room temperature, which obtains from the expression (1). In contrast, the decrease of voltage drop at diode 103 caused by the temperature variation is to the extent of 0.1 volts. Thus, the decrease of voltage drop at the diode 103 is less in comparison with the variation of the gate potential Vg1 of FET 102 caused by the temperature variation. For this reason, the reduction of increasing the gate potential Vg1 is less in this case of the bias circuit of FET shown in FIG. 12.
Accordingly, such a bias circuit of FET does not follow the increase of gate potential caused by increasing the gate current exponentially. Such difficulty is also present in the case of increasing a base potential on the basis of a base current in a bipolar transistor. In addition, there is also difficulty not only for the case of transistor using a compound semiconductor, but also for a transistor using silicon material.